1. Technical Field
The present invention relates to an input receiver, and more particularly, an input receiver capable of converting an external signal to an internal signal of pulse type.
2. Description of Related Art
High-speed semiconductor devices receive an external data through circuits such as a buffer circuit or a latch circuit, etc., to maintain the level of the external data after a sampling operation. Only when such buffering and latching operations are accurately performed, it is assumed that the external data were correctly sampled. Accordingly, high-speed semiconductor devices must quickly perform a series of operations, for example, a buffering operation, a latching operation, and a converting operation of an external signal to generate a desired internal signal. The fast operations can improve an operation frequency of the semiconductor devices.
For instance, digital circuits such as high-speed semiconductor devices buffer an external signal and latch the buffered signal by clocking at a rising edge or a falling edge of a clock pulse to receive an external signal. In particular, input receivers of semiconductor devices receive an external signal and transmit the signal through a pair of data transmission lines TSL/CSL (True Signal Line/Complement Signal Line) by generating and loading pulse type signals of different phases on the transmission lines. Then, the input receivers sample the external signal by using a clock pulse to output a pulse-type internal signal having the same width as the clock pulse.
FIG. 1 is a circuit diagram of a conventional input receiver. Referring to FIG. 1, a conventional input receiver comprises a preamplifier 10, an inverter 12, a phase splitter 14, a clocked sampled amplifier 16, and drivers 22, 23.
The preamplifier 10 comprises PMOS transistors 24, 26 for receiving an external signal Vi and a reference signal Vref at their gates, a PMOS transistor 28 connected between a power source voltage Vdd and the PMOS transistors 24, 26, and NMOS transistors 30, 32 connected between the PMOS transistors 24, 26 and a ground voltage. When the external signal Vi and the reference signal Vref are input to the preamplifier 10, the preamplifier 10 compares the signal Vi with the reference signal Vref to amplify the voltage deference between two signals and output a differential amplified signal OUT to the phase splitter 14 through the inverter 12 (which is connected to an output node of the preamplifier 10).
The phase splitter 14 comprises two inverter chains. One inverter chain drives an input signal from the preamplifier 10 to an output terminal, and the other inverter chain inverts a phase of the input signal and drives it to the output terminal. Accordingly, the phase splitter 14 splits the differential amplified signal OUT into two signals OUT and OUTB and provides the signals to the clocked sampled amplifier 16.
The clocked sampled amplifier l6 comprises a clocked latched amplifier 18 and a pre-charge circuit 20. The clocked latched amplifier 18 comprises a NMOS transistor 38 for receiving at its gate an external clock CLK, NMOS transistors 40, 42 for receiving the outputs OUT and OUTB of the phase splitter 14, a latch circuit (which comprises PMOS transistors 44, 46 and NMOS transistors 48, 50) for amplifying the level difference of the signals OUT and OUTB. A pre-charge circuit 20 comprises two PMOS transistors 34, 36, connected between an output node of the clocked latched amplifier 18 and the power source voltage Vdd, for pre-charging an output of the clocked latched amplifier 18 to a level of the power source voltage Vdd to produce output signals OUT_CB and OUT_TB, respectively. The PMOS transistors 34, 36 are switched in response to the external clock CLK.
The clocked sampled amplifier l6 samples the signals OUT and OUTB in response to the external clock CLK to latch and amplify the two signals, and then provides the amplified signals of pulse type OUT_CB and OUT_TB to an internal circuit through the drivers 22, 23. For instance, when the external clock CLK is logic xe2x80x9clowxe2x80x9d, the pre-charge circuit 20 is driven and the outputs of the clocked latched amplifier 18 are pre-charged to the level of the power source voltage Vdd, thereby the output signals OUT_CB, OUT_TB of logic xe2x80x9chighxe2x80x9d are output from the drivers 22, 23. When the clock CLK transitions from logic xe2x80x9clowxe2x80x9d to logic xe2x80x9chighxe2x80x9d in pre-charging the outputs of the clocked latched amplifier 18, the NMOS transistor 38 turns on to enable the clocked latched amplifier 18 and disable the pre-charge circuit 20. At this time, if the output signals OUT and OUTB of the phase splitter 14 is input to the NMOS transistors 40, 42, the level difference of the signals OUT, OUTB is detected and amplified by the latch circuit in the clocked latched amplifier 18 to output the signals OUT_CB and OUT_TB.
As described above, the conventional input receiver shown in FIG. 1 samples an external signal by enabling the clocked latched amplifier 18 in response to an external clock CLK of logic xe2x80x9chighxe2x80x9d, and pre-charges the outputs of the clocked latched amplifier 18 to a level of the power source voltage Vdd by disabling the clocked latched amplifier 18 and driving the pre-charge circuit 20, in response to the clock CLK of logic xe2x80x9clowxe2x80x9d, to output the signals OUT_CB and OUT_TB as a final output signal of pulse type.
However, the conventional input receiver as shown in FIG. 1 has a predetermined delay time from the time of enabling of the clocked latched amplifier 18 to the time of latch operation, while generating output signals of pulse type by using one stage. In addition, the delay time, which is caused during converting the external signal into a true signal and a complement signal in the preamplifier 10 and the phase splitter 14, greatly varies with a level of an external signal. As a result, a high-speed semiconductor device cannot generate a pulse type internal signal from an external signal having a small swing width and high frequency by using the conventional input receiver. Thus, a need exists for an input receiver that reduces an internal operation time of a semiconductor device by quickly sampling an external signal having a decreasing swing amplitude.
To solve the problems as described above, it is an object of the present invention to provide an input receiver for generating a pulse type internal signal from an external signal having a very small swing.
It is another object of the present invention to provide an input receiver for generating a pulse type internal signal from an external signal having a very small swing voltage in response to a high-speed clock.
It is further object of the present invention to provide an input receiver for sampling and amplifying an external signal in high speed to generate a pair of signals of pulse type.
According to an aspect of the present invention, an input receiver comprises a clock sampled amplifier comprising first and second input/output nodes for receiving an external signal and a reference signal, respectively, in response to a first state of a clock signal and a delayed sampling clock signal, and for amplifying and sampling the voltage difference between the external signal and the reference signal, respectively, in response to a transition of the clock signal and the delayed sampling clock signal to a second state; and a pulse generator comprising first and second output nodes connected between a power source voltage and a ground voltage, for pre-charging the first and second output nodes in response to the first state of the delayed sampling clock signal, and for selectively pulling down one of outputs of the first and second output nodes to a level of the ground voltage to generate a pulse signal, in response to the second state of the delayed sampling clock signal and outputs of the first and second input/output nodes of the clock sampled amplifier.
In one embodiment according to the present invention, the input receiver further comprises a clock generator comprising. The second state of the clock and the delayed sampling clock signals are complementary state of the first state of the clock and the delayed sampling clock signals, respectively.
In one embodiment according to the present invention, the clock sampled amplifier further comprises a latched amplifier, connected between the first and second input/output nodes, for sensing and amplifying the voltage difference between the external signal and the reference signal when the clock signal transitions from the first state to the second state; and first and second pass gates, connected to the first and second input/output nodes, respectively, for receiving the external signal and the reference signal in response to the first state of the delayed sampling clock signal.
In one embodiment according to the present invention, the pulse generator further comprises first and second pre-charge devices, connected between the power source voltage and the first and second output nodes, for pre-charging the first and second output nodes to a level of the power source voltage in response to the first state of the delayed sampling clock signal; a first and second pull-down devices, connected between the first and second input/output nodes in the clock sampled amplifier and the first and second output nodes, for inverting one of the outputs of the first and second output nodes in response to the second state of the delayed sampling clock signal and the outputs of the clock sampled amplifier; and a pull-up amplifier, connected between the first and second output nodes, for pulling up one of the outputs of the first and second output nodes having a higher output voltage.
According to another aspect of the present invention, a method for converting an external signal into an internal signal of pulse type in a semiconductor device is provided. The method comprises the steps of receiving the external signal and a reference signal in response to a first state of a clock signal and a delayed sampling clock signal; amplifying the voltage difference between the external signal and the reference signal to generate two amplified signals in response to a transition of the clock signal to a second state; pre-charging a power source voltage to generate two output signals in response to the first state of the delayed sampling clock signal; and generating a pulse signal by pulling down one of the output signals in response to the amplified signals and a transition of the delayed sampling clock signal to a second state.
Advantageously, a high-speed input receiver of the present invention directly amplifies and samples an external signal without a pre-amplifying operation or a buffer operation. Thus, an input signal can receive an external signal having a small swing level in high speed into a semiconductor device. In addition, because an input receiver does not perform the pre-charging operation, it can amplify an external signal in high speed.